The instruction pipeline of a RISC processor has the following stages

Q. The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB). The IF, ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 35 instructions take 2 clock cycles each, and the remaining 25 instructions take 1 clock cycle each. Assume that there are no data hazards and no control hazards.

The number of clock cycles required for completion of execution of the sequence of instructions is

Ans: 219

Sol:

Given, total number of instructions (n) = 100 
Number of stages (k) = 5 
Since, if n instructions take c cycle, so (c-1) stalls will occur for these instructions. 

Therefore, the number of clock cycles required = Total number of cycles required in general case + Extra cycles required (here, in PO stage),= (n + k – 1) + Extra cycles  = (100 + 5 -1) + 40*(3-1)+35*(2-1)+25*(1-1) = (100 + 4) + 40*2+35*1+25*0 = 104 + 115  = 219 cycles