The size of the physical address space of a processor is 2𝑃 bytes

Q. The size of the physical address space of a processor is 2^𝑃 bytes. The word length is 2^𝑊 bytes. The capacity of cache memory is 2^𝑁 bytes. The size of each cache block is 2^𝑀 words. For a 𝐾-way set-associative cache memory, the length (in number of bits) of the tag field is

(A) 𝑃 − 𝑁 − log₂ 𝐾                                          (B) 𝑃 − 𝑁 + log₂ 𝐾

(C) 𝑃 − 𝑁 − 𝑀 − 𝑊 − log₂ 𝐾                          (D) 𝑃 − 𝑁 − 𝑀 − 𝑊 + log₂ 𝐾

Ans: 𝑃 − 𝑁 + log₂ 𝐾

Sol:

Physical Address Space = 2^P Bytes. Word Length is 2^W bytes, which means each word is of size 2^W bytes.
Cache memory size = 2^N Bytes and Tag Size = 2^X Bytes.
Physical address is P – W bits
Number of blocks in cache = 2^(N-W-M)

It is a K-way set associative cache memory, each set in cache will have K-blocks.
So, Number of sets = 2^(N-W-M)/ K
SET bits will be N-W-M-logk
Offset bits will be M

We know,
TAG bits = Main memory bits – SET bits – offset bits
So, TAG bits(x) = P – W – (N-M-W-logk)- M
      = P – W – N + M + W + logk – M
      x = P – N + logk