In the circuit shown below, assume that the comparators are ideal and all components have zero propagation delay. In one period of the input signal 𝑉𝑖𝑛 = 6 sin(𝜔𝑡)

Q. In the circuit shown below, assume that the comparators are ideal and all components have zero propagation delay. In one period of the input signal 𝑉_𝑖𝑛 = 6 sin(𝜔𝑡), the fraction of the time for which the output OUT is in logic state HIGH is

Sol:

The output represents X-NOR gate.

So, the given diagram can be simplified as

0 ≤ Vin < 3 happens for the period 0 to 30° and 150° to 180° the output is high for, 30 to 150° and 180° to 360° Total period gets high output = 300