The logic gates shown in the digital circuit below use strong pull-down nMOS transistors for LOW logic level at the outputs

The logic gates shown in the digital circuit below use strong pull-down nMOS transistors for LOW logic level at the outputs

Q. The logic gates shown in the digital circuit below use strong pull-down nMOS transistors for LOW logic level at the outputs. When the pull-downs are off, high-value resistors set the output logic levels to HIGH (i.e. the pull-ups are weak). Note that some nodes are intentionally shorted to implement “wired logic”. Such shorted nodes

The logic gates shown in the digital circuit below use strong pull-down nMOS transistors for LOW logic level at the outputs Read More »

In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data

In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data

Q. In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data 𝐷𝑖𝑛 using clock 𝐶𝐾. The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for logic LOW levels. The data bit and clock periods are equal and the value of Δ𝑇/𝑇𝐶𝐾 = 0.15, where the parameters

In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data Read More »

A solar cell of area 1.0 cm2 , operating at 1.0 sun intensity, has a short circuit current of 20 mA

A solar cell of area 1.0 cm2 , operating at 1.0 sun intensity, has a short circuit current of 20 mA

Q. A solar cell of area 1.0 cm2 , operating at 1.0 sun intensity, has a short circuit current of 20 mA, and an open circuit voltage of 0.65 V. Assuming room temperature operation and thermal equivalent voltage of 26 mV, the open circuit voltage (in volts, correct to two decimal places) at 0.2 sun intensity is Ans: 0.59

A solar cell of area 1.0 cm2 , operating at 1.0 sun intensity, has a short circuit current of 20 mA Read More »

A dc current of 26 μA flows through the circuit shown. The diode in the circuit is forward biased and it has an ideality factor of one

A dc current of 26 μA flows through the circuit shown. The diode in the circuit is forward biased and it has an ideality factor of one

Q. A dc current of 26 μA flows through the circuit shown. The diode in the circuit is forward biased and it has an ideality factor of one. At the quiescent point, the diode has a junction capacitance of 0.5 nF . Its neutral region resistances can be neglected. Assume that the room temperature thermal

A dc current of 26 μA flows through the circuit shown. The diode in the circuit is forward biased and it has an ideality factor of one Read More »

Scroll to Top