Memory Organization - Computer System Archiitecture Objective Questions and Answers

(6) A nano control memory is implemented to
[A] improve the speed of execution
[B] reduce the overall control memory size
[C] reduce the complexity of hardware
[D] none of the above

Comment

Answer: Option [B]
(7) In the memory hierarchy the fastest memory is
[A] SRAM
[B] Cache
[C] Registers
[D] DRAM

Comment

Answer: Option [C]

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(8) A memory device in which a bit is stored as a charge across the stray capacitance
[A] SRAM
[B] EPROM
[C] DRAM
[D] Bubble memory

Comment

Answer: Option [C]
(9) Cache memory is implemented using
[A] Dynamic RAM
[B] Static RAM
[C] PROM
[D] EPROM

Comment

Answer: Option [B]
(10) Given a 256*4 RAM chips, how many chips are required to provide a memory capacity of 1 KB of RAM
[A] 1
[B] 8
[C] 4
[D] None of the above

Comment

Answer: Option [A]

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