Memory Organization - Computer System Archiitecture Objective Questions and Answers

Questions

6 A nano control memory is implemented to

A improve the speed of execution

B reduce the overall control memory size

C reduce the complexity of hardware

D none of the above

Answer: Option [B]

7 In the memory hierarchy the fastest memory is

A SRAM

B Cache

C Registers

D DRAM

Answer: Option [C]

⭐ Make GKSeries Your Preferred Source on Google

8 A memory device in which a bit is stored as a charge across the stray capacitance

A SRAM

B EPROM

C DRAM

D Bubble memory

Answer: Option [C]

9 Cache memory is implemented using

A Dynamic RAM

B Static RAM

C PROM

D EPROM

Answer: Option [B]

10 Given a 256*4 RAM chips, how many chips are required to provide a memory capacity of 1 KB of RAM

A 1

B 8

C 4

D None of the above

Answer: Option [A]