GATE

Q. Consider the line integral ∫(𝑥𝑑𝑦 − 𝑦𝑑𝑥) 𝐶 the integral being taken in a counterclockwise direction over the closed curve 𝐶 that forms the boundary of the region 𝑅 shown in the figure below. The region 𝑅 is the area enclosed by the union of a 2 × 3 rectangle and a semi-circle of […]

Q. In the circuit shown, the clock frequency, i.e., the frequency of the Clk signal, is 12 kHz. The frequency of the signal at Q2 is_______kHz. Ans: 4 Solution: let Initial states be Q1 = Q2 = 0

Q. In the circuit shown, 𝑉𝑠 is a square wave of period 𝑇 with maximum and minimum values of 8 V and -10 V, respectively. Assume that the diode is ideal and 𝑅1 = 𝑅2 = 50 Ω. The average value of 𝑉𝐿 is______volts (rounded off to 1 decimal place). Ans: -3.1 – -2.9

Q. Radiation resistance of a small dipole current element of length l at a frequency of 3 GHz is 3 ohms. If the length is changed by 1%, then the percentage change in the radiation resistance, rounded off to two decimal places, is _______________%. Ans: 1.99 – 2.01 Solution:

Q. The baseband signal 𝑚(𝑡) shown in the figure is phase-modulated to generate the PM signal 𝜑(𝑡) = cos(2𝜋𝑓𝑐𝑡 + 𝑘 𝑚(𝑡)). The time 𝑡 on the x-axis in the figure is in milliseconds. If the carrier frequency is 𝑓𝑐 = 50 kHz and 𝑘 = 10𝜋, then the ratio of the minimum instantaneous frequency

Q. If 𝑋 and 𝑌 are random variables such that 𝐸[2𝑋 + 𝑌] = 0 and 𝐸[𝑋 + 2𝑌] = 33, then 𝐸[𝑋] + 𝐸[𝑌] =           . Ans:11 Solution: E[x + y] = E[x] + E[y] E [Ax] = A E[x] Where E [x] represents the expected or mean value of the random variable ‘x’

Q. In the circuit shown, A and B are the inputs and F is the output. What is the functionality of the circuit? (A) Latch (B) XNOR (C) SRAM Cell (D) XOR Ans: XNOR Solution: Case A: A = 0, B = 0 NMOS 1 → OFF NMOS 2 → OFF PMOS 3 → ON

Q. In the circuit shown, what are the values of F for EN = 0 and EN = 1, respectively? (A) 0 and D (B) Hi-Z and D (C) 0 and 1 (D)  Hi-Z and D̅ Ans: Hi-Z and D̅

Q. A standard CMOS inverter is designed with equal rise and fall times (β𝑛 = βp). If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin (𝑁𝑀𝐿) and the HIGH noise margin 𝑁𝑀𝐻? A. 𝑁𝑀𝐿 increases and 𝑁𝑀𝐻 decreases. B. 𝑁𝑀𝐿 decreases and

Q. In the table shown, List I and List II, respectively, contain terms appearing on the left-hand side and the right-hand side of Maxwell’s equations (in their standard form). Match the left-hand side with the corresponding right-hand side. A) 1 – P, 2 – R, 3 – Q, 4 – S                            (B) 1 – Q,